`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/04/30 09:23:03
// Design Name: 
// Module Name: Top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Top
( 
  //ddr4-物理接口
  input             sys_rstn        ,//复位按键
  input             c0_sys_clk_n    ,
  input             c0_sys_clk_p    ,
  output            c0_ddr4_act_n   ,
  output    [16:0]  c0_ddr4_adr     ,
  output    [1:0]   c0_ddr4_ba      ,
  output    [0:0]   c0_ddr4_bg      ,
  output    [0:0]   c0_ddr4_ck_c    ,
  output    [0:0]   c0_ddr4_ck_t    ,
  output    [0:0]   c0_ddr4_cke     ,
  output    [0:0]   c0_ddr4_cs_n    ,
  inout     [7:0]   c0_ddr4_dm_n    ,
  inout     [63:0]  c0_ddr4_dq      ,
  inout     [7:0]   c0_ddr4_dqs_c   ,
  inout     [7:0]   c0_ddr4_dqs_t   ,
  output    [0:0]   c0_ddr4_odt     ,
  output            c0_ddr4_reset_n 
);

//wire define
wire   [00:0]  init_calib_complete;
wire   [31:0]  ud_rdata           ;
wire   [00:0]  ud_rde             ;
wire   [00:0]  ud_rempty          ;
wire   [00:0]  ud_rvs             ;

wire   [31:0]  ud_wdata           ;
wire   [00:0]  ud_wde             ;
wire   [00:0]  ud_wvs             ;
wire   [00:0]  wr_rd_clk          ;

wire   [00:0]  peripheral_aresetn ;

data_test data_test
(
    .resetn       (init_calib_complete),
    .ud_wr_clk    (wr_rd_clk          ),
    .ud_wde       (ud_wde             ),
    .ud_wvs       (ud_wvs             ),
    .ud_wdata     (ud_wdata           ),
    .ud_rd_clk    (wr_rd_clk          ),
    .ud_rde       (ud_rde             ),
    .ud_rempty    (ud_rempty          ),
    .ud_rvs       (ud_rvs             ),
    .ud_rdata     (ud_rdata           )
);


system_wrapper system_wrapper_i
(
    .sys_rst            (~sys_rstn            ),
    .c0_sys_clk_p       (c0_sys_clk_p         ),
    .c0_sys_clk_n       (c0_sys_clk_n         ),
    .c0_ddr4_act_n      (c0_ddr4_act_n        ),
    .c0_ddr4_adr        (c0_ddr4_adr          ),
    .c0_ddr4_ba         (c0_ddr4_ba           ),
    .c0_ddr4_bg         (c0_ddr4_bg           ),
    .c0_ddr4_ck_c       (c0_ddr4_ck_c         ),
    .c0_ddr4_ck_t       (c0_ddr4_ck_t         ),
    .c0_ddr4_cke        (c0_ddr4_cke          ),
    .c0_ddr4_cs_n       (c0_ddr4_cs_n         ),
    .c0_ddr4_dm_n       (c0_ddr4_dm_n         ),
    .c0_ddr4_dq         (c0_ddr4_dq           ),
    .c0_ddr4_dqs_c      (c0_ddr4_dqs_c        ),
    .c0_ddr4_dqs_t      (c0_ddr4_dqs_t        ),
    .c0_ddr4_odt        (c0_ddr4_odt          ),
    .c0_ddr4_reset_n    (c0_ddr4_reset_n      ),

    .init_calib_complete(init_calib_complete  ),
    .peripheral_aresetn (peripheral_aresetn   ),

    .ud_rfifo_rst       (~peripheral_aresetn  ),
    .ud_rdata           (ud_rdata             ),
    .ud_rde             (ud_rde               ),
    .ud_rvs             (ud_rvs               ),
    .ud_rvs_clk         (wr_rd_clk            ),
    .ud_rempty          (ud_rempty            ),

    .ud_wfifo_rst       (~peripheral_aresetn  ),
    .ud_wdata           (ud_wdata             ),
    .ud_wde             (ud_wde               ),
    .ud_wvs             (ud_wvs               ),
    .ud_wvs_clk         (wr_rd_clk            ),
    .wr_rd_clk          (wr_rd_clk            )
);



endmodule
